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JESD204B.01 2012 is a JEDEC interfacing standard for high-speed serial communications of digital radio samples and control data between latest generation of data converters and digital signal processing (DSP) devices including advanced features like deterministic latency and increased throughput. JESD204-B is an RTL controller implementation of the protocol features.

Key Features:

  • Support JESD204B.01 2012 specification
  • Transmitter / Receiver Module
  • Support rates up to 12.5 Gbps
  • Multiple Lanes
  • Multiple Converters
  • ML Mode
  • SL Mode
  • Flexible Sample widths (N)
  • Flexible Sample Envelope (NT)
  • HD Mode
  • Deterministic Latency support
  • Support for any ASIC / ASSP / FPGA target
  • Customization on demand
MTI’s JESD204B solution implements the Transmitter (TX) and Receiver (RX) controller modules for flexible and high performance data transfers up to 12.5 Gbps in compliance with the latest JESD204B.01 2012 standard release. It includes all main features required to support MCDA-ML applications. MTI’s IPC-JESD204B is a self-contained, fully tested solution and it is widely used today in a number of Tier1 applications for ASIC/ASSP and FPGAs devices. Hardware test-bed available based on Altera ArriaVGT, StratixV and Cyclone5 EVMs.

  • Request the datasheet here.