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MTI CPRI 7.0 – now available!!

2016-08-10 08:54:36 MTI CPRI 7.0 is now available!! CPRI (Common Public Radio Interface) is an interfacing standard for high-speed communication of digital radio samples and control data between wireless base station and remote radio modules.

C-RAN and fronthaul

2016-06-20 10:03:17

C-RAN and fronthaul

Several articles on our work within C-RAN and fronthaul are now available in the library: http://www.mti-mobile.com/technology/technical-papers.

FPGA Engineer for MTI Radiocomp ApS

2016-06-10 10:08:21 Link:
  We offer: Do you want to be part of the development of the new future 5G mobile network? Do you want to be part of an international R&D site? Then join MTI Radiocomp. We are an important competence center in the MTI group, working closely with our sister sites in California and Taiwan and with some of the very largest players in the industry. We are building a demonstrator for the remote radio head and base station for our vision of the 5G network. Through the innovative solutions demonstrated, we target to influence upcoming 5G standards. In addition to research work, the FPGA group is responsible for developing and supporting soft intellectual property cores, which are advanced functional modules with our core technology wrapped in a package for international key players in the industry to include in their SoC’s. You will be involved in new development as well as resolving support issues from customers. MTI Radiocomp is a dynamic company with flat structures, innovative culture, with tradition for teamwork and idea sharing. What we expect from you: As an FPGA engineer, you will be introduced to our main technologies and to our FPGA architecture and design flow. You will be working in an energetic, engaged and professional team. You will get exciting challenges and an international atmosphere. Your first challenges will be to learn JESD204B and CPRI to be able to be a part of our support team, and later you will become a part of the development of future technologies for FPGA/ASIC designs. The FPGA design and implementation covers a wide range of technologies. The nature of the business will give you an in depth knowledge of associated signal processing, network technologies and protocols. You will be working closely together with the rest of the FPGA team, our software team and the systems engineering team to reach the most innovative and smart designs. The FPGA team is a part of the HW group and it consists of a highly skilled team distributed in our three locations in Taiwan, California and Denmark. The designs coming out of the team are targeted for FPGAs and for soft IP’s in ASICs. Together with the rest of the team, you will assure consistency and adherence to best practices. You will strive to deliver best quality and continuously improve the state of art FPGA and Soft IP development. You will be reporting to the local manager for the FPGA team. Main tasks for the team:
  • Development of the next generation of FPGA’s for 5G
  • Beginning-to- end FPGA design
  • IP soft core development, maintenance and support for ASICs
  • Integrate algorithms into VHDL modules
  • Support the software team in developing the HW drivers.
  • Give input and discuss with the system engineering team
Technical areas for the team:
  • Signal processing: e.g. FIR filters, Sample Rate Conversion, etc.
  • Protocols: CPRI, OBSAI, JESD204B, Ethernet
  • Coding: Scrambling, 8b10b, 64b/66b and Reed-Solomon
  • Main scripting languages: Tcl, Perl, Batch and Bash.
  • Main tools: Xilinx Vivado and ModelSim
  • Documentation
Personal skills: Personally you strive to make a difference in our products, e.g. within current products and in defining 5G. You are a systematic and solution oriented person that manages to bring structure and proper documentation with your design. You feel motivated by being the best within your field and you get inspired when working in a team. You are open to different cultures and changes in an international environment. Language skills: Written and spoken English at high level. Education Required A Master or Bachelor in Engineering or similar with focus on FPGA/ASIC design, signal processing, as well as knowledge about telecommunication systems and technologies. Work Experience, Specialized Skills and Knowledge Required 0 to 5 years’ experience. As an FPGA engineer, you are expected to have knowledge in FPGA/ASIC design methodologies and flows, and to be proficient in VHDL coding. It is an advantage if you know Verilog as well. In addition, you will use various scripting languages like MatLab, Perl, TCL, Bash, Batch and others in daily activities. Please send your application via the "Ansøg" link. Please write in your application that you've seen the job at Jobfinder

C-RAN tutorial at IEEE ICC 2016

2016-05-23 08:46:22 We are pleased to invite for a tutorial on “Centralized Radio Access Networks: Moving Baseband to the Cloud” which MTI Radiocomp together with Nokia and West Virginia University will give at IEEE ICC 2016.
http://icc2016.ieee-icc.org/content/tutorials#Friday http://icc2016.ieee-icc.org/sites/icc2016.ieee-icc.org/files/u44/T14.pdf

MTI Radiocomp & Altera White Paper: OTN Transport of Baseband Radio Serial Protocols in C-RAN Architecture for Mobile Network Applications

2014-04-14 12:19:36 A new whitepaper developed by MTI Radiocomp & Altera about "OTN Transport of Baseband Radio Serial Protocols in C-RAN Architecture for Mobile Network Applications" is now available at the following link: